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Assembly Source File  |  1995-12-16  |  11.2 KB  |  329 lines
  1.                INCLUDE   "exec/funcdef.i"
  2.                INCLUDE   "exec/exec_lib.i"
  3.                INCLUDE   "macros.i"
  4.                INCLUDE   "shared_defs.i"
  5.  
  6. * $Id: sv_regs30.asm,v 3.5 95/12/16 18:36:06 Martin_Apel Exp $
  7.  
  8.                XDEF      _PFlushA30
  9.                XDEF      _PFlushP30
  10.  
  11.                XDEF      _SetMMUState30
  12.                XDEF      _ReadMMUState30
  13.                XDEF      _SaveMMUState30
  14.                XDEF      _RestoreMMUState30
  15.                XDEF      _GetPageSize30
  16.  
  17.                XDEF      _GenDescr30
  18.  
  19.                XDEF      _ColdRebootPatch
  20.                XREF      _OrigColdReboot
  21.  
  22.                XDEF      _ColdRebootPatchStart
  23.                XDEF      _ColdRebootPatchEnd
  24.                XDEF      _PatchLoc4          ; for ColdRebootPatch
  25.                                              ; after VMM exits
  26.                * A few defines for the MMU registers
  27. TCB_E          EQU       31                  ; Translation control: enable
  28. TCF_E          EQU       (1<<31)
  29. TTB_E          EQU       15                  ; Transparent translation: enable
  30. TTF_E          EQU       (1<<15)
  31. TTB_CI         EQU       10                  ; Transparent translation: cache inhibit
  32. TTF_CI         EQU       (1<<10)
  33. TTF_RW_STAT    EQU       ((1<<9)|(1<<8))
  34. SRB_I          EQU       10                  ; MMUSR: Invalid
  35. SRF_I          EQU       (1<<10)
  36. SRB_T          EQU       6                   ; MMUSR: TT hit
  37. SRF_T          EQU       (1<<6)
  38. PDB_CI         EQU       6                   ; Page descr: cache inhibit
  39. PDF_CI         EQU       (1<<6)
  40. PDB_WP         EQU       2                   ; Page descr: write protected
  41. PDF_WP         EQU       (1<<2)
  42.  
  43.                MACHINE   68030
  44.  
  45.                SECTION   CODE
  46.  
  47. _PFlushA30:    movem.l   a5/a6,-(sp)
  48.                lea       PFlushA30(pc),a5
  49.                move.l    $4,a6
  50.                jsr       _LVOSupervisor(a6)
  51.                movem.l   (sp)+,a5/a6
  52.                rts
  53.  
  54. PFlushA30:     pflusha
  55.                rte
  56.  
  57. ***********************************************
  58.  
  59.                ALIGN_LONG
  60. _PFlushP30:    movem.l   a5/a6,-(sp)
  61.                move.l    12(sp),a0
  62.                lea       PFlushP30(pc),a5
  63.                move.l    $4,a6
  64.                jsr       _LVOSupervisor(a6)
  65.                movem.l   (sp)+,a5/a6
  66.                rts
  67.  
  68.                ALIGN_LONG
  69. PFlushP30:     pflush    #0,#0,(a0)
  70.                rte
  71.  
  72. ***********************************************
  73.  
  74. _SaveMMUState30:
  75.                * Saves the current MMU registers into a private buffer.
  76.                * No inputs, no outputs
  77.                lea       _PrivateMMUState(pc),a0
  78.                move.l    a0,-(sp)
  79.                bsr       _ReadMMUState30
  80.                addq      #4,sp
  81.                lea       _MMUStateValid(pc),a0
  82.                move.w    #1,(a0)
  83.                rts
  84.  
  85. ***********************************************
  86. * The following routines have to stand in this order to copy them
  87. * to a buffer in one go if they should be installed after exit still.
  88.  
  89. _ColdRebootPatchStart
  90. _ColdRebootPatch:
  91. _PatchLoc4     move.l    _OrigColdReboot,-(sp)    * step into RestoreMMU
  92.                and.b     #$7f,$de0002
  93.  
  94. ***********************************************
  95.  
  96. _RestoreMMUState30:
  97.                * Restore the MMU registers from the private buffer.
  98.                * No inputs, no outputs
  99.  
  100.                tst.w     _MMUStateValid(pc)
  101.                beq       Ready
  102.                lea       _PrivateMMUState(pc),a0
  103.                move.l    a0,-(sp)
  104.                bsr       _SetMMUState30
  105.                addq      #4,sp
  106. Ready          rts
  107.  
  108. ***********************************************
  109.  
  110. _MMUStateValid dc.w       0
  111. _PrivateMMUState:
  112.                ds.b       MS30_SIZE
  113.  
  114. ***********************************************
  115.  
  116. _SetMMUState30:
  117.                * Called from C as:
  118.                * void SetMMUState30 (MMUState30*)
  119.  
  120.                movem.l   a5-a6,-(sp)
  121.                move.l    12(sp),a0
  122.                move.l    4,a6
  123.                lea       SetMMUState30(pc),a5
  124.                jsr       _LVOSupervisor(a6)
  125.                movem.l   (sp)+,a5-a6
  126.                rts
  127.  
  128. SetMMUState30: lea       -4(sp),a1                ; reserve long-word on stack
  129.                clr.l     (a1)
  130.                pmove     (a1),TC                  ; MMU ausschalten
  131.  
  132.                pmove     MS30_CRP_HI(a0),CRP
  133.                pmove     MS30_SRP_HI(a0),SRP
  134.                pmove     MS30_TT0(a0),TT0
  135.                pmove     MS30_TT1(a0),TT1
  136.                pmove     MS30_TC(a0),TC           ; MMU einschalten
  137.                PRINT_DEB "MMU registers set"
  138.  
  139.                rte
  140.  
  141. _ColdRebootPatchEnd
  142.  
  143. ***********************************************
  144.  
  145. _ReadMMUState30:
  146.                * Called from C as:
  147.                * void ReadMMUState30 (MMUState30*)
  148.  
  149.                movem.l   a5-a6,-(sp)
  150.                move.l    12(sp),a0                   ; start address of MMUState
  151.                move.l    4,a6
  152.                lea       ReadMMUState30(pc),a5
  153.                jsr       _LVOSupervisor(a6)
  154.                movem.l   (sp)+,a5-a6
  155.                rts
  156.  
  157. ReadMMUState30:
  158.                pmove     TC,MS30_TC(a0)
  159.                pmove     TT0,MS30_TT0(a0)
  160.                pmove     TT1,MS30_TT1(a0)
  161.                pmove     CRP,MS30_CRP_HI(a0)
  162.                pmove     SRP,MS30_SRP_HI(a0)
  163.                rte
  164.  
  165. ***********************************************
  166.  
  167. _GenDescr30:   * This function generates an MMU page descriptor for
  168.                * a given logical address. It includes all the standard
  169.                * information a page descriptor contains. In addition
  170.                * the U bit is misused to detect a transparent translation
  171.                * register hit. This way there is no need for separate
  172.                * handling of cache modes and such for each processor
  173.                * type.
  174.                * C prototype:
  175.                *  ULONG GenDescr (ULONG LogAddr);
  176.  
  177.                movem.l   a5-a6,-(sp)
  178.                move.l    4,a6
  179.                move.l    12(sp),a0
  180.                PRINT_DEB "GenDescr30 called for address %08lx",a0
  181.                lea       GenDescr(pc),a5
  182.                jsr       _LVOSupervisor(a6)
  183.                movem.l   (sp)+,a5-a6
  184.                rts
  185.  
  186. GenDescr:      * If MMU is turned off, no PTEST instruction must be executed.
  187.                sub.w     #4,sp
  188.                pmove     tc,(sp)
  189.                move.l    (sp)+,d0
  190.                btst.l    #TCB_E,d0
  191.                beq       MMUOff
  192.  
  193.                * Check if the address hits into one of the TT registers
  194.                sub.w     #2,sp
  195.                ptestr    #1,(a0),#0
  196.                pmove     mmusr,(sp)
  197.                move.w    (sp)+,d0
  198.                btst.l    #SRB_T,d0
  199.                bne       TTHit
  200.  
  201.                * Check if there is a valid table mapping for this address
  202.                sub.w     #2,sp
  203.                ptestr    #1,(a0),#7,a1
  204.                pmove     mmusr,(sp)
  205.                move.w    (sp)+,d0
  206.                btst.l    #SRB_I,d0
  207.                bne       InvalidTranslation
  208.  
  209.                * there is a valid mapping: Extract the physical address,
  210.                * the WP and cache mode.
  211.                sub.w     #4,sp
  212.                pmove     tc,(sp)
  213.                move.l    (sp)+,d1
  214.  
  215.                movem.l   d2/d3,-(sp)
  216.                and.b     #7,d0          ; mask number of levels
  217.                moveq     #4,d2
  218.                sub.b     d0,d2
  219.                lsl.b     #2,d2          ; * 4
  220.                lsr.l     d2,d1          ; ignore lower TC bits
  221.  
  222.                moveq     #0,d2          ; number of bits taken
  223.                                         ; from upper part of physical address
  224. count_bits     move.l    d1,d3
  225.                lsr.l     #4,d1
  226.                and.b     #$f,d3
  227.                add.b     d3,d2          ; accumulate number of bits
  228.                subq.b    #1,d0
  229.                bne       count_bits
  230.  
  231.                sub.b     #32,d2         ; 32 - number of bits
  232.                neg.b     d2
  233.                moveq     #1,d1          ; generate mask
  234.                lsl.l     d2,d1
  235.                subq.l    #1,d1
  236.                not.l     d1
  237.  
  238.                move.l    (a1),d0        ; take upper x bits from
  239.                and.l     d1,d0          ; virtual address
  240.                not.l     d1
  241.                move.l    a0,d2
  242.                and.l     d2,d1          ; and the rest from the
  243.                or.l      d1,d0          ; logical address
  244.                and.w     #~(PAGESIZE-1),d0
  245.                move.l    (a1),d1
  246.                and.w     #(PDF_CI|PDF_WP),d1      ; don't forget those special
  247.                bset.l    #0,d1                    ; bits
  248.                or.w      d1,d0
  249.                movem.l   (sp)+,d2-d3
  250.                PRINT_DEB "GenDescr30: returns %08lx",d0
  251.  
  252.                rte
  253.  
  254. MMUOff:        * MMU is turned off. Return the logical address as
  255.                * the physical address
  256.                move.l    a0,d0
  257.                and.w     #~(PAGESIZE-1),d0
  258.                bset.l    #0,d0                    ; make resident, cacheable
  259.                rte
  260.  
  261. InvalidTranslation:
  262.                * return illegal descriptor
  263.                moveq     #0,d0
  264.                rte
  265.  
  266. TTHit:         * This address hits into one of the TT registers.
  267.                * Find out which of the two is hit and return the
  268.                * corresponding cache mode and WP status
  269.                movem.l   d2-d4,-(sp)
  270.  
  271.                * First read the TT registers
  272.                sub.w     #8,sp
  273.                pmove     tt0,(sp)
  274.                move.l    (sp)+,d0
  275.                pmove     tt1,(sp)
  276.                move.l    (sp)+,d1
  277.  
  278.                btst.l    #TTB_E,d0
  279.                beq       TT1Hit
  280.                move.l    a0,d4                    ; save address for eor
  281.                move.l    d0,d2                    ; save DTT0 for mask
  282.                move.l    d0,d3                    ; save DTT0 for CM
  283.                eor.l     d4,d0                    ; cmp with TT0
  284.                asl.l     #8,d2                    ; shift mask
  285.                not.l     d2
  286.                and.l     d2,d0                    ; only look at non-masked bits
  287.                and.l     #$ff000000,d0            ; only A31 - A24 valid here
  288.                beq       TT0Hit
  289. TT1Hit:        move.l    d1,d3
  290.  
  291. TT0Hit:        move.l    a0,d0
  292.                and.w     #~(PAGESIZE-1),d0
  293.                or.w      #$9,d0                   ; mark as resident and TT hit
  294.                btst.l    #TTB_CI,d3
  295.                beq       CachingAllowed
  296.                bset.l    #PDB_CI,d0
  297. CachingAllowed and.w     #TTF_RW_STAT,d3
  298.                bne       NotWP
  299.                bset.l    #PDB_WP,d0
  300. NotWP
  301.                movem.l   (sp)+,d2-d4
  302.                rte
  303.  
  304. ***********************************************
  305.  
  306. _GetPageSize30:
  307.                movem.l   a5/a6,-(sp)
  308.                lea       GetPageSize30(pc),a5
  309.                move.l    $4,a6
  310.                jsr       _LVOSupervisor(a6)
  311.                movem.l   (sp)+,a5/a6
  312.                btst.l    #TCB_E,d1
  313.                bne       MMUIsOn
  314.                moveq     #0,d0
  315.                rts
  316. MMUIsOn        moveq     #20,d0
  317.                lsr.l     d0,d1
  318.                and.w     #$f,d1
  319.                moveq     #1,d0
  320.                lsl.l     d1,d0
  321.                rts
  322.  
  323. GetPageSize30: sub.w     #4,sp
  324.                pmove     tc,(sp)
  325.                move.l    (sp)+,d1
  326.                rte
  327.                
  328.                END
  329.